In a field of asynchronous digital transmission, a digital signal is transmitted asynchronously between a signal transmitting apparatus such as a CD transport specialized for playback of a CD (Compact Disc) and a signal receiving apparatus including a D/A (Digital/Analog) converter.
To achieve high quality playback in this case, it is essential to absorb a shift (time difference) between clocks used by the signal transmitting apparatus and the signal receiving apparatus, respectively.
A lot of control systems to achieve it have been proposed conventionally. For example, as shown in FIG. 5, a PLL system is generally known that provides a signal receiving apparatus 20 with a PLL (Phase Locked Loop) circuit 201 to separately generate a clock signal synchronized with a signal transmitting apparatus 10 from a digital input signal transmitted via a signal transmission line 30.
Incidentally, the signal receiving apparatus 20 includes a D/A converter (D/A circuit). The D/A circuit 202 converts the digital input signal from the PLL circuit 201 to generate an analog output signal that is supplied to an audio-visual playback system not shown via a signal line 40.
In addition, as shown in FIG. 6, for example, an SRC system is also known that places at a post-stage of a PLL circuit 201 an SRC (Sampling Ratio Converter) circuit 204, to which a reference clock signal is supplied from a reference clock generating circuit 203, and that generates a clock signal at quartz accuracy anew using the SRC circuit 204. Furthermore, as shown in FIG. 7, for example, a two-way twin link system is known that employs a signal receiving apparatus 20 including a D/A circuit 202 as a master, and that establishes synchronization by supplying a reference clock signal from a reference clock generating circuit 203 to the D/A circuit 202 and by sending it back to a signal transmitting apparatus 10 such as a CD transport via a signal transmission line 50.
Moreover, as shown in FIG. 8, a mass buffering system is known that places at a post stage of a PLL circuit 201 a mass memory circuit 205, to which a reference clock signal is supplied from a reference clock generating circuit 203, and that picks out a clock signal from a digital input signal stored in the mass memory circuit 205 at quartz accuracy.
Incidentally, in FIG. 6-FIG. 8, the same components as those of FIG. 5 are designated by the same reference numerals and their duplicate description is omitted here.
On the other hand, in an image playback field, an application for a time axis correcting apparatus is filed that corrects time axis fluctuations efficiently by avoiding repetition of quantization by reading a signal at every prescribed interval while thinning it out or repeatedly reading it to adjust the time axis of digital data transferred between an image memory and an image input device, thereby generating and outputting a high quality image signal (see Patent Document 1, for example).
Prior Art Document
Patent Document
Patent Document 1: Japanese Patent Laid-Open No. 2006-180441.